VHDL/vivado syntax errors

Question

Write a VHDL module for the Parallel-in, Parallel-out right-shift register of Figure (attached), but add an active-low asynchronous clear signal ClrN. Do not use individual flip-flops in your code. Simulate the module to obtain a timing diagram similar to Figure (attached).

Please use parameters listed below for the waveform generations.

-set ClrN = 1 for 3.5 clock cycles, = 0 for the next half clock cycle, = 1 for rest fo test.

-set L = 1 for 5 clock cycles, = 0 for the next 3 clock cycles, = 1 for the rest of the test

-set SI = 1

-set D = 0101

-set Sh = 0 for 1 clock cycle, = 1 for the next 5 clock cycles, = 0 for the rest of the test

Submit simulation waveforms that demonstrate the operation of your code.

I get error [Synth 8-1789] cannot update 'in' object dout

I've tried the following:

library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity insertname is
port (
    SI, Clk, ClrN, Sh, L : in std_logic;
    Din : in std_logic_vector (3 downto 0);
    SO : out std_logic;
    Dout : std_logic_vector (3 downto 0)
);
end entity insertname;

architecture behavioral of insertname is
    signal temp: std_logic_vector (3 downto 0) := "0000";
begin
    process (Clk, ClrN)
    begin
        if ClrN = '0' then
            temp <= x"0";
        elsif Clk'event and Clk = '1' and Sh = '1' then
            temp <= SI & temp(3 downto 1);
            SO <= temp(0);
        elsif Clk'event and Clk = '1' and Sh = '0' and L = '1' then
            temp <= Din;
        elsif Clk'event and Clk='1' and Sh='0' and L='0' then
            temp <= temp;
        end if;
    end process;
Dout <= temp;
end behavioral;

Figures mentioned above

The linked figures are from Fundamentals of Logic Design 6th ed. by Charles H. Roth, Jr. and Larry L. Kinney, pages 360-361. Note you've made SO a separate flip flop. You can also express the multiplexers shown in front of the flip flops in Figure 12.10 (b) as an inner if statement. You don't need to assign a value to itself in a sequential element (register, flip flops). Note Table 12-1 doesn't show it. Your shift assignment appears incorrect from Figure 12-10(b). — user1155120
– user1155120, Commented Nov 7, 2018 at 23:00

am9417 · Accepted Answer · 2018-11-07 07:39:22Z

4

To fix the syntax error, check the port list in your entity declaration: The Dout signal should be defined as out like this:

Dout : out std_logic_vector (3 downto 0)

As noted by user1155120, IEEE Std 1076-2008, 6.5.2 Interface object declarations states:

If no mode is explicitly given in an interface declaration other than an interface file declaration, mode in is assumed.

edited Nov 7, 2018 at 7:39

answered Nov 7, 2018 at 7:09

am9417

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2 Comments

user1155120 Over a year ago

IEEE Std 1076-2008, 6.5.2 Interface object declarations "If no mode is explicitly given in an interface declaration other than an interface file declaration, mode in is assumed."

am9417 Over a year ago

@user1155120 Thanks, good to know in the future. I have always defined the mode explicitly so this hasn't been an issue.

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