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I've written a simple function which does log2 computation of any integer number and then "ceils" it to the next integer:

function log2ceil(intVal: integer) return natural is
    variable i        : natural;
    variable bitCount : natural;
begin

    i := (intVal - 1);
    bitCount := 0;

    while (i > 0) loop
        bitCount := bitCount + 1;
        i:=shiftRightInt(i,1);
    end loop;

    return bitCount;
end log2ceil;

function shiftRightInt(ValueToShift: integer; NrToShift:natural) return integer is
begin
    return to_integer(shift_right(to_unsigned(ValueToShift, 32), NrToShift));
end shiftRightInt; 

Works, fine. The problem is with the simulation. Every time I try to simulate it with a simple function call in a test bench:

stim: process
begin
    wait for 10 ns;
    log2ceil(3);
    wait;
end process;

it gives me following error:

ERROR: [VRFC 10-1472] type error near log2ceil ; expected type  void 

Why does it expect type Void? And how can I avoid getting this error?

4
  • 2
    A function call is an expression, it returns a value. If you were to supply a Minimal, Complete, and Verifiable example someone could have duplicated the error in another tool that might produce a more expressive error report. In an ideal world you should have gotten an error message telling you log2ceil does not designate a procedure, your usage is a syntax error. (Try assigning the return value of the function call to a variable or signal class object of type integer or a natural). Commented Mar 17, 2016 at 4:52
  • When making a minimal, complete and verifiable example, you can try to reduce the code of the function log2ceil as well or just use another test function. Commented Mar 17, 2016 at 6:23
  • That is a thoroughly bizarre error message from a VHDL compiler! It would make sense for a C compiler, where procedures are simulated using "void functions" so you can call functions and discard the return values. You can't do that in VHDL. Commented Mar 17, 2016 at 12:24
  • @BrianDrummond Multiple HDL front ends, a common IR (not all elements used by every HDL) and a common simulator. The problem is that the VHDL front end didn't catch the syntax error leaving it to be caught by a linking loader rule for SystemVerilog or SystemC. The lack of VHDL standard compliance could represent parser feature 'borrowing' from another HDL - assignment isn't an operator in VHDL, it's a statement. There could be more lurking issues. Commented Mar 17, 2016 at 19:57

2 Answers 2

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Your tool isn't giving a very helpful error message. The problem is that you are referencing a function in log2ceil that has not yet been declared. Given the order you define things, shiftRightInt isn't visible yet.

When I compile your code with Modelsim, I get: `

(vcom-1136) Unknown identifier "shiftRightInt".

Edit: After including your process I got the error @user1155120 pointed out. In Modelsim:

No feasible entries for subprogram "log2ceil".

As user1155120 noted, you are calling a function in a procedure context. You need to assign the return value to something.

First, you can swap the order of declarations. I.e.:

function shiftRightInt(ValueToShift: integer; NrToShift:natural) return integer is
begin
    return to_integer(shift_right(to_unsigned(ValueToShift, 32), NrToShift));
end shiftRightInt;

function log2ceil(intVal: integer) return natural is
    variable i        : natural;
    variable bitCount : natural;
begin

    i := (intVal - 1);
    bitCount := 0;

    while (i > 0) loop
        bitCount := bitCount + 1;
        i:=shiftRightInt(i,1);
    end loop;

    return bitCount;
end log2ceil;

The other is to define a "prototype" of shiftRightInt:

function shiftRightInt(ValueToShift: integer; NrToShift:natural) return integer;

function log2ceil(intVal: integer) return natural is
    variable i        : natural;
    variable bitCount : natural;
begin

    i := (intVal - 1);
    bitCount := 0;

    while (i > 0) loop
        bitCount := bitCount + 1;
        i:=shiftRightInt(i,1);
    end loop;

    return bitCount;
end log2ceil;

function shiftRightInt(ValueToShift: integer; NrToShift:natural) return integer is
begin
    return to_integer(shift_right(to_unsigned(ValueToShift, 32), NrToShift));
end shiftRightInt; 
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2 Comments

the order has nothing to do with it, but the assignment problem is obvious.
With your given example, order does matter. I pointed out the compilation error. Which is why @user1155120 pointed MCVE is essential. And I did edit my answer to include the note about the assigning of the function result.
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The code:

stim: process
begin
  wait for 10 ns;
  log2ceil(3);
  wait;
end process;

is describing a procedure call, but log2ceil is a function. Procedures have a return type of void, whereas your function returns an integer.

You need to provide a dummy variable to collect the return value:

stim: process
  variable dummy : natural;
begin
  wait for 10 ns;
  dummy := log2ceil(3);
  wait;
end process;

The error message is a bit cryptic, but correct!

1 Comment

Procedures have no return value. VHDL has no type void. For another example of the same error message that does not support your hypothesis see Expecting type void for behavioral, caused by two else i that should be elsif`s. The error message has no basis in the VHDL language. void is only found in 18. VHPI access functions describing C information models which doesn't apply in the linked question or here.

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