VHDL Code explanation needed (std_logic_vector)

Question

1) std_logic_vector(data_width - 1 downto 0)

In this code, I am not understanding (-1 downto 0). I know this is telling us that it is 8 bit. But Not understanding how? For example, (7 donwto 0) is self-explanatory eg. 0,1,2,3,4,5,6,7.

2) A_reg(data_width - 1 downto 1) <= A_reg(data_width - 2 downto 0);

I know we are left shifting. But can anyone explain how? I wanted to know how the bit position is changing or shifting.

Oldfart · Accepted Answer · 2020-04-04 15:18:04Z

1

You should read very carefully. It does not say (-1 downto 0). it says (data_width - 1 downto 0).

Thus if data_width is 8 you get (8-1 downto 0) which is your (7 downto 0)

Now the next one: A_reg(data_width - 1 downto 1) <= A_reg(data_width - 2 downto 0);

Again using a data_width of 8 we get : A_reg(7 downto 1) <= A_reg(6 downto 0);

Thus the bits 6,5,4,...0 are transferred to resp bits 7,6,5,..1. Each bit is moved one position to the left, but bit 0 stays the same:

 A[7][6][5][4][3][2][1][0]
     /  /  /  /  /  /  /|
    /  /  /  /  /  /  / | 
   v  v  v  v  v  v  v  v
 A[7][6][5][4][3][2][1][0]

answered Apr 4, 2020 at 15:18

Oldfart

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1 Comment

Amit Over a year ago

Thank you very much. Your explanation is so nice and clear.

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