How to create boolean data type to standard logic in VHDL

Question

Is there an existing function within the regular std.logic library to convert a boolean data type to std logic in vhdl?

I don't think there is, because I don't know for sure how you would expect it to behave. Let's say the conversion function is convert(b : boolean) return std_logic. Then what std_logic values would you expect to result from convert(true) and convert(false)? You could argue that active high and active low logic should give opposite results, so you would want different conversion functions for each case. Conversions in the other direction are even more complicated because you have to decide how to convert 9 different std_logic values to just two boolean values. — Harry
– Harry, Commented Jun 4, 2021 at 8:19

Bananenkönig · Accepted Answer · 2021-06-04 10:33:39Z

-3

The answer in short: no.

As @Harry pointed out, it isn't possible to map 2 values from boolean to 9 values from std_logic.

The std_logic-type is used, among other things, to detect problems in your code whilst simulating and to have a better representation how the hardware will act later on.

So I would recommend you to not write a function which converts true to '1' and false to '0', because then you'll lose the advantage of the std_logic-type.

It is noted, that converting from std_logic to boolean is allowed and even implemented since the VHDL 2008 standard.

answered Jun 4, 2021 at 10:33

Bananenkönig

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