How to print array value in VerilogHDL?

Question

`timescale 1ns/1ps   
module m_top 
(
input GCLK,//100MHz,Y9
input [7:0] i_in1,
output  o_out1,
output reg o_out2,
inout io_data
);

reg hh [2:0][1:0] ;
reg [2:0]hh2[1:0] ;
always @(negedge GCLK)begin
hh[1][1]=3'b1;
$display("%b",hh);//Memory hh is not a legal argument for printing. 
hh2[1][1]=3'b1;
$display("%b",hh2);// Memory hh2 is not a legal argument for printing. 
end
endmodule

I want to know the value of hh in Verilog 2011(not system verilog),but is not a legal argument for printing,how to achieve it?

dave_59 · Accepted Answer · 2025-07-28 20:18:22Z

1

Verilog 1364-2005 (the last version of the IEEE Verilog standard) does not allow accessing more than one element of an array at a time, which SystemVerilog does. You would need to a for loop to iterate through each dimension of the array.

reg hh [2:0][1:0];

initial begin
  integer i, j;
  for (i = 0; i < 3; i = i + 1) begin
    for (j = 0; j < 2; j = j + 1) begin
      $display("hh[%0d][%0d] = %b", i, j, hh[i][j]);
    end
  end
end

SystemVerilog has the %p format specifier for pretty printing aggregates like unpacked multidimensional arrays and structs.

edited Jul 28 at 20:18

answered Jul 28 at 15:28

dave_59

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