context
I'm making a simulation environment with systemC co-simulated with verilog/VHDL RTL modules using modelsim/questasim
My Verilog modules use parameters to set up each module My VHDL modules use generics to set up each module My systemC modules can replicate this using templates if needed.
The following discussion is very alike except I can't use the sc_main because of Modelsim: Setting the vector length in SystemC with a received parameter
Question
I want to be able to instantiate a systemC module using a verilog parameter
Example
Here is a minimal (not-working) example :
Verilog file
module submodule
#(
parameter parameter1 = 32
}
(
input logic clk,
/* signals (...) */
);
systemc_module
#(
.parameter_sc (parameter1 * 2) /* parameter can be modified */
)
systemc_module_0
(
.clk(clk),
/* signals (...) */
);
endmodule
SystemC file
SC_MODULE(systemc_module)
{
sc_in<sc_logic> clk;
sc_signal<sc_lv<parameter_sc> > compilation_dynamic_signal;
// other signals (...)
SC_CTOR(systemc_module)
{
// I can get the parameter at execution time with modelsim :
int buf;
sc_get_param("parameter_sc", buf)
}
}
/*Modelsim module export*/
SC_MODULE_EXPORT(systemc_module);
