I am asking about standard Verilog 2001 and not System Verilog extensions. I was sure it was listed as an advantage of tasks, over a function. However, I have this syntax working and it seems to at least simulate well.
{index, value} = sample(val1, val2, operation);
It seems the single bus is not a limitation if it is unpacked to multiple wires? The function needs a similar sample = {fIndex, fValue}; to construct the multiple values. Will synthesis tools have an issue with this?
x,y,z,r,theta,real,imaginaryare possible.