Questions tagged [system-verilog]
In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.
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Non overlapped implication(|=>) used in system verilog assertion
I know that if I use
s1 |=> s2
the consequent sequence expression s2 will be evaluated on the next clock tick. However, if there is no clock(combinational ...
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System Verilog Adapter Interface
I am using Xilinx's PCIe Core, which in its latest version duplicates the AXI valid signal 22 times.
This means writing something like {22{1'b1}} every time I try ...
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What do the terms code coverage and functional coverage refer to when it comes to digital design verification
It seems that verifying a design is a more complex task than the actual design itself and takes a lot longer to carry out. We may even need to create testbench to very the original testbench that ...
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Modelling current to remain in particular range for fixed simulation time
I am a novice in SystemVerilog. I wish to know how to model a 8-bit signal X to attain four levels for certain ranges of time. For example,let the legal values of X be from 40 to 80(40 < X < 80)
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Why the port type of this module default to 'var'?
In "IEEE Std 1800-2012 SystemVerilog", p. 668, I find this:
module mh11(output integer x); // output var integer x
I wonder why it is default to 'var' but not '...
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Generate flip-flops using only combinational logic
Just for fun, I wanted to design and simulate D-type flip-flops using only combinational logic in Verilog (or SystemVerilog). I am using using Verilator for the simulation.
My initial attempt, which ...
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Creating SystemVerilog module using for loop and separate custom module
I am trying to create an n-bit barrel shifter using the diagram in the answer to this question: https://stackoverflow.com/questions/26551049/vhdl-n-bit-barrel-shifter
I've read that if the variable ...
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Spawning threads in SystemVerilog with input variables
I run onto a rather confusing situation where I was writing a code for a UVM monitor. This module performs these operations in order:
Listen to channel (virtual interface) until intercepting one or ...
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Functional and Timing accuracy of an RTL Model
I am sometimes really confused by the abusive use of jargon in EDA/VLSI design articles and books. With no precise definitions, its upto the reader to make interpretation which is very ambiguous and ...
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Inheritance of properties
Is it possible to inherit some properties from the scope that we invoke a function? A code snippet might help more to explain:
...
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Secure signals on boot time to prevent unwanted operations
How can I be sure that at boot time my module won't get random values to it's control signals and write to an address* before I reset the module?
*(or anything that shouldn't be done before reset)
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What is the difference between testing and verification?
Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction.
To ...
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I need help with verilog code, I am in trouble?
I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I ...
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How should this code look like in verilog?
I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me ...
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using C libraries inside verilog
I'm implementing a radio in Verilog. the time taken for bit reversal while computing the FFT is more. it is almost equal to a symbol time (OFDM system). Can I use a FFT library in C, which can be ...
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Efficient use of space in FPGA
Background and clarifications:
I've never developed/written a single piece of hardware before, but I'm currently using Verilog to develop a huge project for a FPGA as my final graduation project.
I'...
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Difference between >> and >>> in verilog?
What is the difference between >> and >>> in verilog/system verilog? I know that ...
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Difference between >> and >>> [duplicate]
What's the difference between >> and >>> in Verilog/SystemVerilog?
I know that ...
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What is wrong with following Verilog code where I am trying to pass a one-dimensional array?
What is wrong with following Verilog code where I am trying to pass a one-dimensional array?
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Difference between HVL and HDL
Hardware description language describes our circuit but what does Hardware Verification Language do? How does it verify the design?
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Single Die Roll Counter Wrap Around Nested Ternary Conditional
I have to emulate a single die roll, therefore it needs to wrap back to one at 6.
`D1 and `D6 correspond to my 3-bit state ...
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Instantiating Parameterized Modules in SystemVerilog
In SystemVerilog I would love to instantiate modules like
...
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Understanding combinational feedback loops
Please give me a simple example of a verilog code that results in combo feedback loop.
Why are these feedback loops undesired in your design? How to interpret blocking vs non blocking assignments in ...
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Why delays cannot be synthesized in Verilog?
I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code.
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How to design a two-stage synchronizer with a clock divider in Verilog?
I have a very fast clock called CLOCK_50 which I would like to slow down through the use of a clock divider. The output is clock....
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Random number generation
I have written this code in system verilog to generate fifty 12-bit random numbers and write them to a file.
How can I generate the random numbers in octal instead of decimal?
Also, how can I make ...
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Is it fine to have different number of input/output port in module and module instant in verilog?
For example if i am going to model T flip flop using D flip flop. I am not writing the whole code of T flip flop as here it is not related to my query.
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How exactly does SystemC/SystemVerilog make the verification flow less laborious task
Now days SystemC or SystemVerilog are used for verification of complex designs, especially for things like SoC designs that are really complex. I do know that these languages bring in the OOP design ...
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How to efficiently implement a single output pulse from a long input on Altera?
I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only ...
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How do I make use of multipliers to generate a simple adder?
I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
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Instantiating multidimensional array in system verilog
I want to create an array in systemverilog which has n entries of m bits.
logic [n-1:0] arr [m-1:0]; (a)
Is this the right way to do it? What if I change the ...
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How to reference subsets of logic[31:0] in SystemVerilog?
(I have two questions for you at the end.)
I'm using SystemVerilog to do various exercises (for personal edification) in Digital Design and Computer Architecture's chapter 7. I'm using Altera's ...
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Working of Prefix Adder
I am trying to understand the working of Brent Kung adder, but I have not been able to.
All that I see in tutorials is just the figure above for carry generation. Can anybody explain it to me with an ...
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System verilog on Quartus synthesis issue
module blockingbad(input logic clk,a,b,c,output logic y);
logic x;
always_ff @(posedge clk) begin
y=x|c;
x=a&b;
end
endmodule
For ...
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Correctly printing from SystemVerilog DPI
I have some verilog VPI code that I'm porting to use SystemVerilog DPI, to be run in Modelsim and Verilator.
In VPI, I use vpi_printf() for debugging and status information. This doesn't work when ...
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Connected to Multiple Drivers Problem Verilog
After I synthesize it, the error occured like this:
...
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Why does this Verilog counter design code have a syntax error?
I am a beginner in Verilog, and I am trying to design a counter. My aim is to increment the count value whenever I press the switch sw. But, I am getting a syntax ...
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Help with $readmemb
I have three variables, x,y,z which acts as an input to my SV model. Each of the input are of 16bit length binary data and I have 500 values of them. I need to supply them as input to my module at ...
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Continuous assignment during SystemVerilog simulation
I am providing input to an SPI interface. The input signal is a concatenation of several different signals. What I would like to do in simulation is have continuous concatenation of the different ...
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System Verilog seq.ended or seq.triggered
Some verification tools support the following System Verilog code:
wire s = seq.ended;
Where seq is an SVA sequence. Other tools do not support this code. Is ...
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Systemverilog to Verilog translation
I have a code block (multiple files) in Systemverilog. I am using the Xilinx tool flow that does not understand SystemVerilog (an old part). Is there a tool (or a rule book) I can use to convert the ...
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Does iverilog support SystemVerilog keywords?
I was running a test case for iverilog provided at this link and had posted a question earlier. When I tested iverilog with uart test case further, found that in uart_tb.v, we are using file uart_port....
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Parameterized net width in Verilog
Is something like this possible ?
parameter width;
wire[width-1] a_net = (width)'b0;
I basically need a variable to control the width of the right hand side. I ...
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Verilog: $display with _ separator
In Verilog, one can conveniently use _ anywhere in binary and hexadecimal literals. For example, 8'b0101_0011 and ...
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Is SystemVerilog string manipulation synthesisable?
I learnt that SystemVerilog provides a string datatype, which allows for many string operations, such as comparison, concatenation, length, etc.
Are those string operations synthesisable?
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