Verilog Muliple if else not working as expected

Question

I am using three buttons on the Altera DE0 Board.

I declare it as

    input [2:0] Button;
    reg [2:0] y;
    parameter [2:0] S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;

I have a nested if-else statement based on the values of the three buttons

always@(negedge (&Button))
//if(&Button == 0)
begin
if(Button == 3'b011)   // Button 2 is pressed
begin
if(y == S0)
    begin
    y = S1;
    end
end
else if(Button == 3'b101)  // Button 1 is pressed
begin
if (y == S1)
    begin
    y = S2;
    end
else if (y == S2)
    begin
    y = S3;
    end
end
else if(Button == 3'b110)  //This is the check on button 0, but this conditional statement does not work. 
begin
if(y == S2)
    begin
    y = S3;
    end
end
end

assign z =  (y == S0);     // z,z1,z2,z3 are LED's on the board
assign z1 = (y == S1);
assign z2 = (y == S2);
assign z3 = (y == S3);

When I use the first two buttons of the if-else statement (button == 3'b011 and button == 3'b101) labeled BUTTON2 and BUTTON1 on the DE0 board, the code works and y changes to the proper value as expected.

But when I try the third button in the if-else, Button == 3'b011, labeled BUTTON0 on the DE0, nothing happens, y does not get the expected value. I used 2 different DE0 boards and the same issue arises.

I think it has something to do with the

always@(negedge (&button))

in that the third button press is just not being detected. But when I use code like

always@(negedge button[0] or negedge button[1] or negedge button[2])

other issues arise that I haven't been able to resolve.

Community · Accepted Answer · 2017-05-23 12:11:11Z

2

You need to think about what hardware you are trying to model. always @(negedge or more generally edge triggered always blocks, are used to imply flip-flops which are generally driven by a clock and reset.

Data signals can be used as clocks as you would in a Frequency Divider. However your use of a unary & a combinatorial reduction operator will result in a glitchy clock in real hardware.

I mentioned thinking about what hardware you are implying because you have this construct:

always@(negedge button[0] or negedge button[1] or negedge button[2])

Which has no equivalent in hardware.

You may find this Altera FSM example helpful. You likely what to implement edge detection from this question so you only change state once per button press.

edited May 23, 2017 at 12:11

CommunityBot

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answered Apr 5, 2014 at 20:04

Morgan

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