6,394 questions
0
votes
1
answer
86
views
Parallel shift of 4-bits by 1 clock cycle, simulation of delay on Verilog
I want to implement the following timing diagram (the numbers here are arbitrary, the main thing is the general principle). In my task a sequence of 4-bit data. This sequence must be written to ...
- 134
1
vote
1
answer
65
views
Use if-generate structure to define two variations of a function, and call that function in the same tb
Here is a small tb, with some example code, where I am trying to define a function two ways, then call that fn below its definition.
module tryfact;
localparam FUNCTION_IS_STATIC = 1;
...
- 2,620
1
vote
1
answer
218
views
Verilog module instance named after different module type
I’m somewhat new to Verilog, and have inherited a project created by someone else. It uses a module instantiation technique for which I don't understand the intent. Basically two different module ...
- 13
3
votes
2
answers
218
views
Does Verilog automatically convert Behavioral modeling into Structural modeling?
I'm a junior Electronic Engineering student currently learning Verilog. I've been studying various modeling methods in Verilog, including Structural, Dataflow, and Behavioral modeling. I have a ...
- 33
0
votes
1
answer
68
views
String triple quotes not getting accepted by simulators
Triple-quoted strings are supported as per IEEE 1800-2023 LRM, but none of the simulators are able to compile (getting the below error). Any lead will help me to understand it better.
module top;
...
- 1,264
1
vote
1
answer
277
views
UVM testbench for APB driver run_phase logic
In the driver_class run_phase code below, I am not able to understand how to write the logic to send the transaction to the DUT.
Can we give Penable, Psel, Pready values manually in the driver class ...
- 19
0
votes
1
answer
203
views
Verilog always @(posedge clk) doesn't work
I want to introduce a one-cycle delay to valid_dat by using @(posedge clk) but it doesn't work. The counter works fine with the clock and increases by one every clock cycle. But valid_delay changes ...
- 61
1
vote
1
answer
133
views
Difference between variables defined with ascending vs. descending indexes
Does it make a difference if you define indexes in descending or in ascending order at the outset?
Specifically, suppose I have the following items defined in a module:
output [7:0] o_RX_Byte;
reg [7:...
-1
votes
1
answer
34
views
what does this grammar mean? "wire test_net = mubi4_test_true_strict(scanmode_i)"
Any one knows what does this definition mean?
"wire test_net = mubi4_test_true_strict(scanmode_i)"
i don't understand the meaning of such usage.
usually the wire is defined just like blow in ...
-1
votes
1
answer
81
views
Testbench for writing to the file in Verilog
This is my Testbench for a design and I am applying inputs to the design using the function '$readmemb'.
I have opened a file using '$fopen' and wish to write the result 'out' in the file named 'jaja....
- 1
1
vote
2
answers
148
views
Not sure why the method "name" is not available
I was trying to understand better how enums and standard methods work.
I compile the code with iverilog -g 2012 example.sv in Icarus Verilog version 11.0 (stable).
I get the error sorry: Enumeration ...
- 1,387
1
vote
1
answer
85
views
4-bit counter that increments after every second: simulation always shows xxxx at the output
Here's my code:
//`timescale 1ns / 1ps
module FourBitLedToggle(
input res,
input Clk,
output [3:0] led
);
reg [27:0] count;//for 1 second check
reg clk1s;//1 second clock
...
1
vote
1
answer
55
views
Why sequence_out is xx in the 2-bit up-counter testbench?
I'm trying to write a 2-bit up-counter in Verilog, and it must have dff in it's design. But, when I test it, outputs are = xx. Can you please help me to fix it?
module dff(d,clk,q);
input d,clk;
...
0
votes
1
answer
375
views
How can I schedule multiple inputs into an instantiated SystemVerilog module?
I am trying to build a module that takes a 32 bit input (parameterised) and outputs the cube of the input. The naive approach would be the following:
module cuber #(
BW = 32
) (
input logic [...
- 3
1
vote
1
answer
53
views
SystemVerilog not reading data correctly
The data read from A_arr, B_arr and C_arr are incorrect.
The value I have in Moddelsim is not what I defined in the testbench.
I have a testbench for my design. It should fetch inputs from A_arr and ...
- 61
0
votes
1
answer
625
views
Creating a ".vvp" file in verilog (using vsCode)
I've been trying to compile a ".v" file into a ".vvp" file but, when i code and run in terminal, i doesn't run. Here the module code, test bench code and the terminal code:
//...
0
votes
1
answer
721
views
Icarus Verilog Syntax error "I give up" for NAND gate
I am getting the error message below.
./nand.v:1: syntax error
I give up.
Here is my nand.v code:
module nand (A, B, C);
input A, B;
output C;
assign C = ~(A & B);
endmodule
And ...
-1
votes
2
answers
63
views
Synthesizable Verilog to dual write a 1-D flop array
I'd like some Verilog (for synthesis) advice. I need dual writes to a 1-D array of flops. Both writes can occur on the same clock, and the write addresses will never be the same when the write enables ...
- 15
0
votes
1
answer
137
views
Sign fixed point arithmetic
Can you please help me with the arithmetic of binary numbers in fixed-point format.
I have two sign-magnitude 8-bit numbers, for example, 0_0101010 and 1_0001100, where the most significant bit ...
- 13
1
vote
1
answer
29
views
Unable to read "wr_en, fifo_in" data using module instantiation
Is there anything wrong with my instantiation?
8 to 32 bit converter is working fine.
Input to fifo is read only when wr_en is high.
wr_en is connected to output signal of valid_q (when valid_q=1, ...
- 11
1
vote
0
answers
347
views
Array slices are not supported for continuous assignment
I'm trying to index into a 2D array in Verilog like this:
`include "src/elementwise_multiplication.v"
module parallel_elementwise_multiplication_dynamic #(parameter N = 8, parameter M = 2) (
...
- 19
1
vote
1
answer
1k
views
How to specify AUTO_TEMPLATE wild card for inputs and outputs separately?
The common practice for auto instantiating a verilog module with wildcard is:
/* sub AUTO_TEMPLATE (
.\(rg_.*\) (\1_@),
); */
sub sub
(/*AUTOINST*/);
The wildcard in the example above says &...
- 880
0
votes
1
answer
163
views
localparam for case values with don't cares. Is 1'b? legal?
Can you replicate, concatenate a '?' literal somehow? It seems my tools accept it.
Most direct answer: Section 3.5 Numbers of 1364-2005 has a stanza for 'z_digits'. z_digit ::= z | Z | ?, so it is ...
- 22.7k
0
votes
1
answer
493
views
Verilog how does assign statement work with a conditional operator?
I am a newbie with Verilog. While doing a lab assignment (yes, I've read the homework policy here), I came across a conditional statement (ternary operator).
assign w1 = load ? in : out;
I understand ...
- 5,237
1
vote
1
answer
438
views
SystemVerilog parameter override unsigned
As per IEEE-1800-2012, 23.10 Overriding module parameters :
A value parameter with a range specification, but with no type
specification, shall have the range of the parameter declaration and
shall ...
- 35
1
vote
2
answers
111
views
Does {128 - 32{1'b0} } mean 96'b0?
I am using PHY using GTH example Verilog code.
In the example code, there is an assign statement.
{128-P_TX_USER_DATA_WIDTH{1'b0}}
If P_TX_USER_DATA_WIDTH = 32, the above code becomes {128 - 32{1'b0}}...
- 11
0
votes
1
answer
633
views
Verilator: How to create a library ( a .a or .so file) from multiple .sv files?
I've got several .sv files that need to be put into a single library (probably a .so or .a file), for example a directory that has the following .sv files:
control.sv hotstate.sv microcode.sv ...
- 8,873
1
vote
2
answers
147
views
Wire conditionally instantiated with generate is not visible later
I'm seeing failing errors both from iverilog and verilator in a module which has a wire instantiated based on a condition. This was originally happening in a SystemVerilog module I got from someone ...
- 8,873
0
votes
1
answer
113
views
Assign a SV port
I am wondering if this systemVerilog syntax is behaviorally correct :
module m (input [3:0] in1);
endmodule
module top();
assign inst.in1 = 4'b1010;
m inst (.in1());
endmodule
I am asking ...
- 35
1
vote
1
answer
76
views
Multiple driver Nets Error for Carry Lookahead Adder
I just began learning SystemVerilog and now am trying to code a Carry Lookahead Adder. However, I kept getting the "Multiple driver Nets" error for the C signal I have.
The error goes like ...
- 11
1
vote
1
answer
57
views
Missing data while shuffling
I'm working on shuffling input Datas using multiplexers and D flipflops. While simulating it, I'm getting one delay in between which makes the next data to disappear.
Here is the Verilog code (for ...
-1
votes
1
answer
207
views
Getting this: Null object access
Am getting this Error the below error, as of my knowledge as per this error message am going to access an empty object.
Error-[NOA] Null object access
generator.sv, 23
The object at dereference ...
- 19
0
votes
3
answers
514
views
Can Verilog functions access variables declared outside the function block?
There is a reg variable containing huge data array. This variable is declared and initialized inside a module.
I created a function inside the Verilog module to access this external data. Surprisingly,...
- 13
2
votes
2
answers
60
views
How can I calculate a generate loop control value from a module parameter?
I have a module which has an integer parameter. This parameter controls a generate loop. When the parameter value is 0, then it cannot be used but must be replaced by 1. I tried to use a function, but ...
1
vote
1
answer
77
views
Verilog code output is always zzz using carry lookahead adder
I am trying to make a multiplier using carry lookahead adder, but the half of my output is zzzz. Here is a part of my code. The cla16 is a 16-bit carry lookahead adder. It is producing zz at output in ...
- 19
1
vote
2
answers
474
views
Is it possible to write task/function inside an interface?
Inside the interface, usually we declare clocking blocks and modports. Is it possible to declare any task or function inside the interface?
If yes, tell me any example scenario.
- 19
0
votes
1
answer
139
views
Verilog code getting X for the signals in the simulation
I am new to verilog and I have two Verilog modules and a main.v module that is a topmodule and I want to simulate it with vivado xilinx. This is my main module. When I try to simulate it, I get X ...
- 45
-1
votes
1
answer
108
views
Register increments twice within a non blocking always
I want to do an up-counter which has an output enable (when high the up-counter is supposed to count up at each clock cycle, otherwise it keeps its previous value). In order to achieve visible results ...
- 408
-2
votes
1
answer
96
views
Cannot get modules to connect properly using wire connections through a finite state machine (FSM)
My project is essentially a song player that doesn't actually output sound but instead outputs the note (i.e. A, G, D, B) on the Basys 3 FPGA 7-segment display with the specified timing using flags.
I'...
1
vote
1
answer
55
views
Getting Incorrect output for Layered Testbench for a Full Adder
I have designed a Full-Adder just to get hands-on Layered Testbench Methodology for a Full-Adder with the Design, Interface, Transaction Class, Generator Class, Driver Class, Monitor Class, Scoreboard ...
- 11
1
vote
2
answers
687
views
Parameterizable/generic Verilog functions
I need to port a large (synthesizable) VHDL-93 code library to Verilog-2005.
I'm very familiar with VHDL, but new to Verilog.
Many things map clearly between the two languages, but I'm completely ...
- 946
-1
votes
1
answer
922
views
Why is "Set as Top-Level Entity" grayed out in quartus?
I am new to hardware design using System Verilog, so I'm trying to compile a very very simple file: a D Flip Flop.
it consists of the following code (taken from https://www.chipverify.com/verilog/...
- 1
1
vote
2
answers
132
views
Assign a Verilog output state from that of a register
I am new to Verilog. I keep getting this error in vivado programming a basys3 board: Vivado Error
here is my Verilog code, It is a simple state machine that changes state on each clock cycle. below ...
- 11
-1
votes
1
answer
72
views
Discrepancy in behavior between different implementations of adder module in Verilog multiplier and divider
I'm encountering a puzzling issue with my Verilog code involving a multiplier and divider. I've implemented both modules using a parallel adder component, but I'm getting different results depending ...
-1
votes
1
answer
84
views
Assignment to two different wires with a bit and its complement yields the same value
I am currently creating a control unit for a pipelined processor using Verilog. I'm using combinatorial assignment using wires. Since I have only limited instructions to support, I have decided to ...
1
vote
2
answers
424
views
Which bits do I need to extract in a signed fixed point multiplier?
I need to design a fixed point multiplier in Verilog that takes in a 16 bif formatted with one sign bit, 6 integer bits and 7 fractional bits. I just can't figure out which bits to extract to ensure ...
- 161
0
votes
1
answer
270
views
How to provide a status to questa vsim on detected test harness issue?
I had existing test benches with icarus verilog. I am exploring questa. The test benches can be called individually or batched. With icarus it provides an extension to have a non-zero return code. ...
- 22.7k
0
votes
1
answer
357
views
Rounding down the absolute value of signed fixed point numbers in Verilog
Context
Hello, I am working on building a R2MDC-FFT engine in Verilog.
Currently, the engine outputs are exhibiting rounding errors (it is failing some provided testcases by a small margin), and I ...
- 13
0
votes
1
answer
256
views
parameter is not declared error. parameters file is not found. in vivado 2022.1
I am getting this error message in vivado 2022.1 when I run the behavioral simulation:
ERROR: [VRFC 10-2989] 'PIPELINES' is not declared [F:/githubccsds/ccsds123-master/ccsds123-master/project/project....
-1
votes
1
answer
534
views
how to write a library file
I'm trying to learn synthesizing with yosys.Im working with verilog now.
I know we need a library file for it, and I have written a .v file for it. how do I convert this into a .lib file? In other ...
